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Reconfigurable Networks-on-Chip

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Kataloginformation
Feldname	Details
Vorliegende Sprache	eng
Hinweise auf parallele Ausgaben	395916992 Buchausg. u.d.T.: ‡Reconfigurable networks-on-chip
ISBN	978-1-4419-9340-3
Name	Chen, Sao-Jie
Name	Lan, Ying-Cherng
Name ANZEIGE DER KETTE	Lan, Ying-Cherng
Name	Tsai, Wen-Chung
Name	Hu, Yu-Hen
T I T E L	Reconfigurable Networks-on-Chip
Verlagsort	New York, NY
Verlag	Springer New York
Erscheinungsjahr	2012
Erscheinungsjahr	2012
Umfang	Online-Ressource (XIII, 203p. 116 illus, digital)
Reihe	SpringerLink. Bücher
Notiz / Fußnoten	Includes bibliographical references and index
Weiterer Inhalt	Reconfigurable Networks-on-Chip; Foreword; Preface; Contents; Part I Introduction to Network-on-Chip; 1 Communication Centric Design; 1.1…Communications-Centric Design Concept; 1.1.1 Multi-Processor System-on-Chip; 1.1.2 Conventional on-Chip Communication Scheme; 1.1.3 Emergence of Network-on-Chip; 1.2…Concept of Network-on-Chip; 1.3…Layers in a Network-on-Chip Design; 1.3.1 Physical Layer; 1.3.2 Network Layer; 1.3.3 Application Layer; 1.4…Motivation and Contributions; 1.4.1 Motivation; 1.4.2 Contributions; 1.5…Organization of Book Chapters; References; 2 Preliminaries. 2.1…Background Knowledge2.2…Conventional Network-on-Chip Architecture; 2.3…Conventional Router Architecture; 2.4…Flow-Control Mechanism; 2.4.1 Packet-Buffer Flow-Control; 2.4.2 Wormhole Flow-Control Based Router; 2.4.3 Virtual-Channel Flow-Control Based Router; 2.5…Routing and Arbitration Techniques; 2.5.1 Problem Decomposition; 2.5.2 State-of-the-Art; 2.6…Quality-of-Service Control; 2.6.1 Connection-Oriented Scheme; 2.6.2 Connection-Less Scheme; 2.7…Reliability Design; 2.7.1 Failure Types in NoC; 2.7.2 Reliability Design in NoC; 2.8…Energy-Aware Task Scheduling; References. Part IINetwork-on-Chips DesignMethodologies Exploration3 Techniques for High Performance Noc Routing; 3.1…NoC Routing Basics; 3.1.1 Characterization of NoC Routing; 3.1.2 Deadlock and Livelock Issues; 3.1.3 Deadlock-Free Routing Schemes in NoCs; 3.2…Turn Model Based Routing Basics; 3.2.1 Odd--Even Turn Model; 3.2.2 Odd--Even Turn-Model Based Routing Algorithm, ROUTE; 3.2.3 Motivations of our Proposed Turn Model Based Routing Schemes; 3.3…Proposed Turn-Model Based Fully Adaptive Routing; 3.3.1 Turn Prohibitions Release; 3.3.2 Path Prohibitions Release. 3.3.3 Deadlock Freedom and Livelock Freedom3.3.4 Fault Tolerance Advantage; 3.3.5 Performance Evaluation; 3.3.5.1 Effects of Fully Adaptive Routing; 3.3.5.2 Effects of Buffer Size; 3.4…Remarks; References; 4 Performance-Energy Tradeoffs for Noc Reliability; 4.1…Reliability in NoC; 4.2…State-of-the-Art Reliable NoC; 4.3…Fault Modeling; 4.4…Energy Consumption in an NoC Architecture; 4.4.1 Derivation of Energy Metrics; 4.4.2 Effect of Retransmission Buffer; 4.4.3 Re-Calculation of Energy per Useful Bit; 4.5…Experimental Results; 4.5.1 Experiments Setup. 4.5.2 Error Control Codes used in Experiments4.5.3 Results Analysis; 4.6…Remarks; References; 5 Energy-Aware Task Scheduling for Noc-Based DVS System; 5.1…Problem Formulation; 5.1.1 Application and Architecture Specification; 5.1.2 Generalized Energy-Aware Task Scheduling Problem; 5.1.3 Dynamic Voltage Scaling; 5.2…Motivational Example; 5.3…Proposed Algorithmic Solution; 5.3.1 Task PrioritizationTask Prioritization; 5.3.2 Task AssignmentTask Assignment; 5.3.3 Power Optimization; 5.3.4 Re-Scheduling Setup; 5.4…Experimental Results; 5.5…Remarks; References. Part III ?Case Study: Bidirectional NoC(BiNoC) Architecture
Titelhinweis	Buchausg. u.d.T.: ‡Reconfigurable networks-on-chip
ISBN	ISBN 978-1-4419-9341-0
Klassifikation	TJFC
	TEC008010
	621.3815
	TK7888.4
Kurzbeschreibung	Annotation, This book provides a comprehensive survey of recent progress in the design and implementation of Networks-on-Chip. It addresses a wide spectrum of on-chip communication problems, ranging from physical, network, to application layers. Specific topics that are explored in detail include packet routing, resource arbitration, error control/correction, application mapping, and communication scheduling. Additionally, a novel bi-directional communication channel NoC (BiNoC) architecture is described, with detailed explanation. Written for practicing engineers in need of practical knowledge about the design and implementation of networks-on-chip; Includes tutorial-like details to introduce readers to a diverse range of NoC designs, as well as in-depth analysis for designers with NoC experience to explore advanced issues; Describes a variety of on-chip communication architectures, including a novel bi-directional communication channel NoC. From the Foreword:Overall this book shows important advances over the state of the art that will affect future system design as well as R & D in tools and methods for NoC design. It represents an important reference point for both designers and electronic design automation researchers and developers.--Giovanni De Micheli
1. Schlagwortkette	System-on-Chip
1. Schlagwortkette	Chip-Multiprozessor
ANZEIGE DER KETTE	System-on-Chip -- Chip-Multiprozessor
SWB-Titel-Idn	356115380
Signatur	Springer E-Book
Bemerkungen	Elektronischer Volltext - Campuslizenz
Elektronische Adresse	$uhttp://dx.doi.org/10.1007/978-1-4419-9341-0
Internetseite / Link	Volltext

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