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Heterogeneous Multicore Processor Technologies for Embedded Systems
Kategorie Beschreibung
036aXD-US
037beng
087q978-1-4614-0283-1
100 Uchiyama, Kunio
104bArakawa, Fumio
108bKasahara, Hironori
112bNojiri, Tohru
116bNoda, Hideyuki
120bTawara, Yasuhiro
124bIdehara, Akio
128bIwata, Kenichi
132bShikano, Hiroaki
331 Heterogeneous Multicore Processor Technologies for Embedded Systems
410 New York, NY
412 Springer New York
425 2012
425a2012
433 Online-Ressource (XI, 224p. 192 illus, digital)
451bSpringerLink. Bücher
501 Description based upon print version of record
517 Heterogeneous Multicore Processor Technologies for Embedded Systems; Preface; Acknowledgments; Contents; Chapter 1: Background; 1.1 Era of Digital Convergence; 1.2 Heterogeneous Parallelism Based on Embedded Processors; References; Chapter 2: Heterogeneous Multicore Architecture; 2.1 Architecture Model; 2.2 Address Space; References; Chapter 3: Processor Cores; 3.1 Embedded CPU Cores; 3.1.1 SuperH TM RISC Engine Family Processor Cores; 3.1.2 Ef ficient Parallelization of SH-4; 3.1.2.1 Highly Effi cient Instruction Set Architecture; 3.1.2.2 Microarchitecture Selections. 3.1.5 Ef fi cient Parallelization of SH-4 FPU3.1.5.1 Floating-Point Architecture Extension; 3.1.5.2 Implementation of Extended Floating-Point Architecture; 3.1.5.3 Performance Evaluation with 3D Graphics Benchmark; 3.1.6 Ef fi cient Frequency Enhancement of SH-X FPU; 3.1.6.1 Floating-Point Architecture Extension; 3.1.6.2 High-Frequency Implementation of the SH-X FPU; 3.1.6.3 Performance Evaluation with 3D Graphics Benchmark; 3.1.7 Multicore Architecture of SH-X3; 3.1.7.1 SH-X3 Core Speci fi cations; 3.1.7.2 Symmetric Multiprocessor (SMP) Support; 3.1.7.3 Asymmetric Multiprocessor Support. 3.3.2 MX-23.4 Video Processing Unit; 3.4.1 Introduction; 3.4.2 Video Codec Architecture; 3.4.2.1 Architecture Model; 3.4.2.2 Stream Domain and Image Domain Processing; 3.4.2.3 Shift-Register-Based Bus Network and Macroblock-Level Pipeline Processing; 3.4.2.4 Hierarchical Power Management; 3.4.2.5 Memory Management; 3.4.3 Processor Elements; 3.4.3.1 Stream Processor; 3.4.3.2 Programmable Image Processing Element; 3.4.4 Implementation Results; 3.4.5 Conclusion; References; Chapter 4: Chip Implementations; 4.1 Multicore SoC with Highly Ef fi cient Cores; 4.2 RP-1 Prototype Chip. 4.2.1 RP-1 Speci fi cations. 3.1.2.3 Asymmetric Superscalar Architecture3.1.2.4 Pipeline Structure of Asymmetric Superscalar Architecture; 3.1.2.5 Zero-Cycle Data Transfer; 3.1.2.6 Early-Stage Branch; 3.1.2.7 Performance Evaluations; 3.1.3 Ef fi cient Frequency Enhancement of SH-X; 3.1.3.1 Microarchitecture Selections; 3.1.3.2 Improved Superpipeline Architecture; 3.1.3.3 Branch Prediction and Out-of-Order Branch Issue; 3.1.3.4 Low-Power Technologies of SH-X; 3.1.3.5 Performance Evaluations; 3.1.4 Frequency and Ef fi ciency Enhancement of SH-X2; 3.1.4.1 Frequency Enhancement of SH-X2; 3.1.4.2 Low-Power Technologies of SH-X2. 3.1.8 Ef fi cient ISA and Address-Space Extension of SH-X43.1.8.1 SH-X4 Core Speci fi cations; 3.1.8.2 Ef fi cient ISA Extension; 3.1.8.3 Address-Space Extension; 3.1.8.4 Data Transfer Unit; 3.2 Flexible Engine/Generic ALU Array (FE-GA); 3.2.1 Architecture Overview; 3.2.2 Arithmetic Blocks; 3.2.3 Memory Blocks and Internal Network; 3.2.4 Sequence Manager and Con fi guration Manager; 3.2.5 Operation Flow of FE-GA; 3.2.6 Software Development Environment; 3.2.7 Implementation of Fast Fourier Transform on FE-GA; 3.3 Matrix Engine (MX); 3.3.1 MX-1; 3.3.1.1 Architecture Overview; 3.3.1.2 PE Design
527 Buchausg. u.d.T.ISBN: 978-1-461-40283-1
540aISBN 978-1-4614-0284-8
540aISBN 1-280-79467-4 ebk
540aISBN 978-1-280-79467-4 MyiLibrary
700 |TJFC
700 |TEC008010
700b|621.3815
700b|004.16
700c|TK7888.4
750 Akio
753 To satisfy the higher requirements of digitally converged embedded systems, this book describes heterogeneous multicore technology that uses various kinds of low-power embedded processor cores on a single chip. With this technology, heterogeneous parallelism can be implemented on an SoC, and greater flexibility and superior performance per watt can then be achieved. This book defines the heterogeneous multicore architecture and explains in detail several embedded processor cores including CPU cores and special-purpose processor cores that achieve highly arithmetic-level parallelism. The authors developed three multicore chips (called RP-1, RP-2, and RP-X) according to the defined architecture with the introduced processor cores. The chip implementations, software environments, and applications running on the chips are also explained in the book. Provides readers an overview and practical discussion of heterogeneous multicore technologies from both a hardware and software point of view;Discusses a new, high-performance and energy efficient approach to designing SoCs for digitally converged, embedded systems;Covers hardware issues such as architecture and chip implementation, as well as software issues such as compilers, operating systems, and application programs;Describes three chips developed according to the defined heterogeneous multicore architecture, including chip implementations, software environments, and working applications.
012 365268445
081 Uchiyama, Kunio: Heterogeneous Multicore Processor Technologies for Embedded Systems
100 Springer E-Book
125aElektronischer Volltext - Campuslizenz
655e$uhttp://dx.doi.org/10.1007/978-1-4614-0284-8
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