| Vorliegende Sprache |
eng |
| ISBN |
978-3-030-38795-2 |
| 978-3-030-38797-6 |
| 978-3-030-38798-3 |
| Name |
Jain, Saurabh ¬[VerfasserIn]¬ |
| Lin, Longyang ¬[VerfasserIn]¬ |
| Name ANZEIGE DER KETTE |
Lin, Longyang ¬[VerfasserIn]¬ |
| Name |
Alioto, Massimo ¬[VerfasserIn]¬ |
| T I T E L |
Adaptive Digital Circuits for Power-Performance Range beyond Wide Voltage Scaling |
| Zusatz zum Titel |
From the Clock Path to the Data Path |
| Auflage |
1st ed. 2020. |
| Verlagsort |
Cham |
| Cham |
| Verlag |
Springer International Publishing |
| Imprint: Springer |
| Erscheinungsjahr |
2020 |
| 2020 |
| 2020 |
| Umfang |
1 Online-Ressource(XVI, 168 p. 113 illus., 107 illus. in color.) |
| Reihe |
Springer eBook Collection |
| Titelhinweis |
Erscheint auch als (Druck-Ausgabe)ISBN: 978-3-030-38795-2 |
| Erscheint auch als (Druck-Ausgabe)ISBN: 978-3-030-38797-6 |
| Erscheint auch als (Druck-Ausgabe)ISBN: 978-3-030-38798-3 |
| ISBN |
ISBN 978-3-030-38796-9 |
| Klassifikation |
TJFC |
| TEC008010 |
| 621.3815 |
| Kurzbeschreibung |
Introduction to wide voltage scaling, applications and challenges -- Reconfigurable microarchitectures down to pipestage and memory bank level -- Automated design flows and run-time optimization for reconfigurable microarchitectures -- Case studies of reconfigurable microarchitectures: accelerators, microprocessors and memories -- Reconfigurable clock networks, automated design flows, run-time optimization and case study -- Conclusion. |
| 2. Kurzbeschreibung |
This book offers the first comprehensive coverage of digital design techniques to expand the power-performance tradeoff well beyond that allowed by conventional wide voltage scaling. Compared to conventional fixed designs, the approach described in this book makes digital circuits more versatile and adaptive, allowing simultaneous optimization at both ends of the power-performance spectrum. Drop-in solutions for fully automated and low-effort design based on commercial CAD tools are discussed extensively for processors, accelerators and on-chip memories, and are applicable to prominent applications (e.g., IoT, AI, wearables, biomedical). Through the higher power-performance versatility techniques described in this book, readers are enabled to reduce the design effort through reuse of the same digital design instance, across a wide range of applications. All concepts the authors discuss are demonstrated by dedicated testchip designs and experimental results. To make the results immediately usable by the reader, all the scripts necessary to create automated design flows based on commercial tools are provided and explained. Provides extensive coverage of the challenges and the key technologies enabling wide power-performance range in digital sub-systems (e.g., processors, memories, accelerators); Includes in-depth description of silicon-proven methodologies to design reconfigurable data path and clock path; Describes techniques for reconfigurable microarchitectures, down to the pipestage and the clock repeater level; Uses a highly interdisciplinary approach covering the circuit, the microarchitectural and the system levels of abstraction; Presents practical design examples and the related methodologies; Offers complementary design files and scripts, useful to replicate the presented developments and develop new designs. |
| SWB-Titel-Idn |
1691523445 |
| Signatur |
Springer E-Book |
| Bemerkungen |
Elektronischer Volltext - Campuslizenz |
| Elektronische Adresse |
$uhttps://doi.org/10.1007/978-3-030-38796-9 |
| Internetseite / Link |
Resolving-System |
| Siehe auch |
Cover |
