| Vorliegende Sprache |
eng |
| Hinweise auf parallele Ausgaben |
514872225 Erscheint auch als (Druck-Ausgabe): ‡Designing with Xilinx® FPGAs |
| ISBN |
978-3-319-42437-8 |
| Name |
Churiwala, Sanjay ¬[Hrsg.]¬ |
| T I T E L |
Designing with Xilinx® FPGAs |
| Zusatz zum Titel |
Using Vivado |
| Verlagsort |
Cham |
| Verlag |
Springer |
| Erscheinungsjahr |
2017 |
| 2017 |
| Umfang |
Online-Ressource (X, 260 p. 141 illus., 3 illus. in color, online resource) |
| Reihe |
SpringerLink. Bücher |
| Titelhinweis |
Erscheint auch als (Druck-Ausgabe): ‡Designing with Xilinx® FPGAs |
| Printed editionISBN: 978-3-319-42437-8 |
| ISBN |
ISBN 978-3-319-42438-5 |
| Klassifikation |
TJFC |
| TEC008010 |
| 621.3815 |
| TK7888.4 |
| ST 190 |
| Kurzbeschreibung |
This book helps readers to implement their designs on Xilinx® FPGAs. The authors demonstrate how to get the greatest impact from using the Vivado® Design Suite, which delivers a SoC-strength, IP-centric and system-centric, next generation development environment that has been built from the ground up to address the productivity bottlenecks in system-level integration and implementation. This book is a hands-on guide for both users who are new to FPGA designs, as well as those currently using the legacy Xilinx tool set (ISE) but are now moving to Vivado. Throughout the presentation, the authors focus on key concepts, major mechanisms for design entry, and methods to realize the most efficient implementation of the target design, with the least number of iterations |
| 2. Kurzbeschreibung |
State of the Art Programmable Logic -- Vivado Design Tools -- IP Flows -- Gigabit Transceivers -- Memory Controllers -- Processor Options -- Vivado IP Integrator -- SysGen for DSP -- Synthesis -- C Based Design -- Simulation -- Clocking -- Stacked Silicon Interconnect -- Timing Closure -- Power Analysis and Optimization -- System Monitor -- Hardware Debug -- Emulation Using FPGAs -- Partial Reconfiguration & Hierarchical Design |
| 1. Schlagwortkette |
Field programmable gate array |
| Logische Programmierung |
| Graphische Programmierung |
| ANZEIGE DER KETTE |
Field programmable gate array -- Logische Programmierung -- Graphische Programmierung |
| SWB-Titel-Idn |
479370877 |
| Signatur |
Springer E-Book |
| Bemerkungen |
Elektronischer Volltext - Campuslizenz |
| Elektronische Adresse |
$uhttp://dx.doi.org/10.1007/978-3-319-42438-5 |
| Internetseite / Link |
Volltext |
