| Vorliegende Sprache |
eng |
| ISBN |
978-90-481-9303-5 |
| Name |
Borrione, Dominique |
| T I T E L |
Advances in Design Methods from Modeling Languages for Embedded Systems and SoC’s |
| Zusatz zum Titel |
Selected Contributions on Specification, Design, and Verification from FDL 2009 |
| Verlagsort |
Dordrecht |
| Verlag |
Springer Science+Business Media B.V |
| Erscheinungsjahr |
2010 |
| 2010 |
| Umfang |
Online-Ressource (VIII, 248 p, digital) |
| Reihe |
Lecture Notes in Electrical Engineering ; 63 |
| Notiz / Fußnoten |
Includes bibliographical references and index |
| Weiterer Inhalt |
Advances in Design Methodsfrom Modeling Languages for Embedded Systems and SoC's; Preface; Contents; Part I UML and MDE for Embedded Systems; Chapter 1:IP-XACT Components with Abstract Time Characterization; Chapter 2:MDE Support for HW/SW Codesign: A UML-based Design Flow; Part II C/C++-Based System Design; Chapter 3:Checkpoint and Restore for SystemC Models; Chspter 4:Efficient Approximately-Timed Performance Modeling for Architectural Exploration of MPSoCs; Chapter 5: Fast SystemC Performance Models for the Exploration of Embedded Memories. Chapter 6:Another Take on Functional System-Level Design and ModelingChapter 7:Design Automation Model for Application-Specific Processors on Reconfigurable Fabric; Chspter 8: A SystemC Superset for High-Level Synthesis; Part III Embedded Analog and Mixed-Signal System Design; Chapter 9:Design of Experiments for Effective Pre-silicon Verification of Automotive Electronics; Chspter 10:A VHDL-AMS Modeling Methodology for Top-Down/Bottom-Up Design of RF Systems; Part IV Assertion Based Design, Verification & Debug; Chspter 11:High Level Synthesis Using Operation Properties. Chapter 12:A Re-Use Methodology for Formal SoC Protocol Compliance VerificationChapter 13:ISIS: Runtime Verification of TLM Platforms; Chapter 14:SMT-based Stimuli Generation in the SystemC Verification Library; Index; |
| Titelhinweis |
Buchausg. u.d.T.ISBN: 978-90-481-9303-5 |
| ISBN |
ISBN 978-90-481-9304-2 |
| Klassifikation |
TJFC |
| TEC008010 |
| *68M99 |
| 68-06 |
| 00B25 |
| 621.3815 |
| 621.392 |
| TK7888.4 |
| Kurzbeschreibung |
More than ever, FDL is the place for researchers, developers, industry designers, academia, and EDA tool companies to present and to learn about the latest scientific achievements, practical applications and users experiences in the domain of specification and design languages. FDL covers the modeling and design methods, and their latest supporting tools, for complex embedded systems, systems on chip, and heterogeneous systems. FDL 2009 is the twelfth in a series of events that were held all over Europe, in selected locations renowned for their Universities and Reseach Institutions as well as the importance of their industrial environment in Computer Science and Micro-electronics. In 2009, FDL was organized in the attractive south of France area of Sophia Antipolis. together with the DASIP (Design and Architectures for Signal and Image Processing) Conference and the SAME (Sophia Antipolis MicroElectronics ) Forum. All submitted papers were carefully reviewed to build a program with 27 full and 10 short contributions. From these, the Program Committee selected a shorter list, based on the evaluations of the reviewers, and the originality and relevance of the work that was presented at the Forum. The revised, and sometimes extended versions of these contributions constitute the chapters of this volume. Advances in Design Methods from Modeling Languages for Embedded Systems and SoC`s presents extensions to standard specification and description languages, as well as new language-based design techniques and methodologies to solve the challenges raised by mixed signal and multi-processor systems on a chip. It is intended as a reference for researchers and lecturers, as well as a state of the art milestone for designers and CAD developers. TOC:Part I, UML and MDE for Embedded Systems.- Part II, C/C++-Based System Design.- Part III, Embedded Analog and Mixed-Signal System Design.- Part IV, Assertion Based Design, Verification Debug. |
| SWB-Titel-Idn |
329517775 |
| Signatur |
Springer E-Book |
| Bemerkungen |
Elektronischer Volltext - Campuslizenz |
| Elektronische Adresse |
$uhttp://dx.doi.org/10.1007/978-90-481-9304-2 |
| Internetseite / Link |
Volltext |
| Siehe auch |
Volltext |
| Siehe auch |
Cover |
| Siehe auch |
Inhaltsverzeichnis |
| Siehe auch |
Einführung/Vorwort |
| Siehe auch |
Inhaltstext |
