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Creating Assertion-Based IP

Creating Assertion-Based IP
Kataloginformation
Feldname Details
Vorliegende Sprache eng
Hinweise auf parallele Ausgaben 276076532 Buchausg. u.d.T.: ‡Foster, Harry D.: Creating assertion-based verification IP
ISBN 978-0-387-36641-8
Name Foster, Harry D.
Krolnik, Adam C.
Name ANZEIGE DER KETTE Krolnik, Adam C.
T I T E L Creating Assertion-Based IP
Verlagsort Boston, MA
Verlag Springer US
Erscheinungsjahr 2008
2008
Umfang Online-Ressource (digital)
Reihe SpringerLink. Bücher
Titelhinweis Buchausg. u.d.T.: ‡Foster, Harry D.: Creating assertion-based verification IP
ISBN ISBN 978-0-387-68398-0
Klassifikation TJFC
TEC008010
621.3815
621.381548
TK7888.4
ZN 4030
Kurzbeschreibung This book presents formal testplanning guidelines with examples focused on creating assertion-based verification IP. It demonstrates a systematic process for formal specification and formal testplanning, and also demonstrates effective use of assertions languages beyond the traditional language construct discussionsNote that there many books published on assertion languages (such as SystemVerilog assertions and PSL). Yet, none of them discuss the important process of testplanning and using these languages to create verification IP. This is the first book published on this subject.
2. Kurzbeschreibung "Assertion-based IP is much more than a comprehensive set of related assertions. It is a full-fledged reusable and configurable transaction-level verification component, which is used to detect both interesting and incorrect behaviors. Upon detecting interesting or incorrect behavior, the assertion-based IP alerts other verification components within a simulation environment, which are responsible for taking appropriate action. The focus of this book is to bring the assertion discussion up to a higher level and introduce a process for creating effective, reusable, assertion-based IP, which easily integrates with the user's existing verification environment, in other words the testbench infrastructure. The guiding principles promoted in this book when creating an assertion-based IP monitor are: modularity-assertion-based IP should have a clear separation between detection and action clarity-assertion-based IP should be written initially focusing on capturing intent (versus optimizations) A unique feature of this book is the fully worked out, detailed examples. The concepts presented in the book are drawn from the authors' experience developing assertion-based IP, as well as general assertion-based techniques. Creating Assertion-Based IP is an important resource for design and verification engineers. From the Foreword: Creating Assertion-Based IP 'reduces to process the creation of one of the most valuable kinds of VIP: assertion-based VIP. This book will serve as a valuable reference for years to come.""Andrew Piziali, Sr. Design Verification EngineerCo-Author, ESL Design and Verification: A Prescription for Electronic System Level MethodologyAuthor, Functional Verification Coverage Measurement and Analysis"
1. Schlagwortkette Integrierte Schaltung
Verifikation
ANZEIGE DER KETTE Integrierte Schaltung -- Verifikation
SWB-Titel-Idn 276331222
Signatur Springer E-Book
Bemerkungen Elektronischer Volltext - Campuslizenz
Elektronische Adresse $uhttp://dx.doi.org/10.1007/978-0-387-68398-0
Internetseite / Link Volltext
Siehe auch Cover
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